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Processing Techniques for 3-D Integration Techniques

S. Burkett, D. Temple*, B. Stoner*, C. Craigie, X. Qiao, G. McGuire*
Department of Electrical Engineering, Boise State University, Boise, ID 83725
*MCNC, Research Triangle Park, NC  27709

Processing techniques that address the interconnect issues required for fabrication of deep sub-micron electronic devices and for three-dimensional (3-D) integration of these components will be described.  As the interconnect density increases, alternate methods of providing input/output (I/O) leads on a chip are required.  One attractive approach to providing increased connectivity is to use through-wafer interconnects.  This reduces the interconnect density on the front surface while providing additional I/Os on the back surface.  This also provides a convenient mechanism to integrate two or more silicon die or heterogeneous integration of silicon with GaAs or HgCdTe to form a 3-D integrated structure.  Processing techniques under development include: high aspect ratio silicon etching, insulator lining, adhesion/barrier layer deposition, seed layer deposition, electroplating, and chemical mechanical planarization (CMP).
The primary obstacles to implementing 3-D stacking are the inability to form high aspect ratio interconnects with a sufficiently small diameter and, consequently, with sufficiently high density, and the lack of techniques compatible with CMOS technology that can be executed within the thermal budget of completed ICs. The approaches to overcoming these obstacles will be described.
This project is supported by the DARPA MTO office and administered by SPAWAR SYSCEN/San Diego, CA under G rant N66001-00-1-8950.

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